CH392F Ethernet Protocol Stack Controller SPI and UART bus QFN28

Description

Overview CH392 is an Ethernet protocol stack management chip, which is used for Ethernet communication in MCU system. CH392 has 10M Ethernet Media Access Control (MAC) and Physical Layer (PHY), is fully compatible with IEEE802.3 protocol, and has built-in Ethernet stack firmware such as IP, DHCP, ARP, ICMP, IGMP, UDP and TCP. MCU system can perform network communication conveniently through CH392. CH392 supports two communication interfaces: SPI interface or asynchronous serial port. Controllers such as DSP/MCU/MPU can control CH392 for Ethernet communication through any of the above communication interfaces. Features ● Internal Ethernet MAC layer and PHY layer. ● Support 10M, full/half duplex self-adaption, and be compatible with 802.3 protocol. ● Support automatic MDI/MDIX line conversion. ● Built-in TCP/IP protocol stack, and support IPv4, DHCP, ARP, ICMP, IGMP, UDP and TCP protocols. ● Provide 4 independent Socket pairs, simultaneously transmit and receive data. ● Provide SPI device interface with the maximum speed of 8MHz, and support SPI serial bus connected to MCU. ● Provide UART with the maximum speed of 921,600bps, support UART connected to MCU, and support the dynamic adjustment of communication baud rate. ● Built-in 4KB RAM can be used for Ethernet data transmission and receiving, and each Socket transceiver buffer can be freely configured. ● Provide QFN28 package. Datasheet